Computer Organization
Q191.
Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = -(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)- is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination \longleftarrow source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.Q192.
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:Q193.
If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations R1 \rightarrow M[100] M[100] \rightarrow R2 M[100] \rightarrow R3 can be replaced byQ194.
A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?Q195.
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:Q196.
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed isQ197.
Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction "bbs reg, pos, labbel" jumps to label if bit in position pos of register operand reg is one. a register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented. temp\rightarrowreg & mask Branch to label if temp is non-zero The variable temp is a temporary register. For correct emulation the variable mask must be generated byQ198.
Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? I. It must be a trap instruction II. It must be a privileged instruction III. An exception cannot be allowed to occur during execution of an RFE instructionQ199.
Consider the following Assembly language program MVIA 30 H ACI 30 H XRA A POP H After the execution of the above program, the contents of the accumulator will beQ200.
A processor that has the carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be: